There is a possibility that the on-resistance can be largely reduced by preparing a high withstand voltage power device using SiC as a semiconductor material. For example, according to a press release by Rohm Co., Ltd., the on-resistance of SiC MOSFETs that Rohm plans to mass-produce can be half the on-resistance of silicon IGBTs with the same withstand voltage class. See Development of low-loss SiC power MOSFET of 1/40 of the conventional one!, at http://www.rohm.co.jp/news/sicpower-j.html. MOSFETs with high withstand voltage containing SiC as the major material are expected to be marketed from semiconductor manufacturers within the next two years. If the cost reduction and improvements in electrical characteristics are achievable, it is thought that the greater part of Si IGBTs in an inverter part will be substituted with SiC IGBTs.
SiC can largely reduce the on-resistance because it has a high insulation breakdown field, even when its drift layer is thinner than an Si device. Thus, it is possible to realize the same withstand voltage as that in the Si device. Moreover, since the doping concentration of the drift layer can be increased, it is possible to reduce the resistance of the drift layer by double digits or more as compared with Si. It is known that the insulation breakdown field of SiC has strong anisotropy. Thus, it is considered that the insulation breakdown field in a <0001> direction is high. Accordingly, in a device wherein a voltage is applied in a direction vertical to a major face of a substrate, namely a depth direction of the device, the major face having a {0001} face is preferable because the insulation breakdown field is high and the resistance of the drift layer can be reduced.
In Si high withstand voltage devices, the resistance of the drift layer accounts for the greater part of the on-resistance. In contrast, with respect to the on-resistance of SiC devices, as described previously, the resistance of the drift layer is reduced so that the influence of the resistance of MOS channels becomes relatively large. In particular, since the state of an SiO2/SiC interface as good as compared with that of an SiO2/Si interface, the MOS channel mobility on the SiO2/SiC interface is approximately one digit smaller than that of the SiO2/Si interface. Accordingly, in SiC high withstand voltage devices, it is important to reduce the on-resistance caused by the MOS channels.
The MOS channel resistance is in proportion to the channel length and in inverse proportion to the channel mobility. Accordingly, to reduce the MOS channel resistance, it is important to select the face azimuth or the formation condition of a gate oxide film so as to obtain high channel mobility and to shorten the channel length. For the sake of reducing the MOS channel resistance, a device structure in which a number of channels are integrated in the same area is preferable. Such a device structure includes a trench MOS structure. According to the trench MOS structure, a number of channels can be integrated without generating parasitic resistance, such as a JFET effect.
FIG. 8 is a cross-sectional view showing the configuration of a general vertical trench MOSFET. As illustrated in FIG. 8, an n-type withstand voltage layer 2 is stacked on one of the major faces of an n-type SiC substrate 1, and a p-type body layer 3 is further stacked thereon. An n-type source contact region 4 and a p-type body contact region 5 adjacent thereto are provided on the p-type body layer 3. A trench 6 penetrates through the n-type source contact region 4 and the p-type body layer 3 and reaches the n-type withstand voltage layer 2. A side wall face and a bottom face of the trench 6 are covered with a gate oxide film 7. A gate electrode 8 is embedded inside the gate oxide film 7 within the trench 6. An upper side of the gate electrode 8 is covered with an interlayer insulation film 9. A source electrode 10 comes into ohmic contact with both the n-type source contact region 4 and the p-type body contact region 5. A drain electrode 11 comes into ohmic contact with the other major face of the n-type SiC substrate 1.
Now, if the doping concentration of a drift layer (n-type withstand voltage layer 2) is increased, a depletion layer is liable to be elongated even in the body region (p-type body layer 3) coming into contact with the drift layer when applying a reverse voltage. To avoid the occurrence of a phenomenon where the body region becomes a so-called punch-through state of being completely depleted, it is required to increase the doping concentration of the body region or to thicken the body region. It is known, however, that increasing the doping concentration of the body region decreases the channel mobility of MOS channels as formed in the body region, as is disclosed in Japanese Patent No. 3610721, which is a counterpart of U.S. Pat. No. 6,057,558. For that reason, there remains an upper limit in the doping concentration of the body region, making it impossible to increase the doping concentration of the body region exceeding that upper limit. Also, where the trench side wall face is vertical to the major face of the substrate, the channel length of a trench MOSFET is equal to the thickness of the body region. Since the thickness of the body region is determined by the desired withstand voltage, it is impossible to shorten the channel length of a trench MOSFET.
The aforementioned patents disclose that when the trench side wall face on which MOS channels are formed is a flat face, a high channel mobility is obtained. However, when the trench side wall face is not vertical to the major face of the substrate (i.e., inclined), the channel length of a MOSFET along the trench side wall face becomes longer than the thickness of the body region. Accordingly, even if the channel mobility is high, the channel resistance cannot be always reduced.
For example, for the purpose of increasing the channel mobility of a MOS device, it has been proposed to form a gate oxide film and a gate electrode on a (03-38) face, as disclosed in JP-A-2002-261275. The (03-38) face is a face that is angled by 54.7 degrees from a (0001) face. Accordingly, when the (0001) face is the major face and the trench side wall face is the (03-38) face, the trench side wall face becomes inclined at an angle of 54.7 degrees from the major face. In this case, the channel length is approximately 1.2 times the thickness of the body region because it becomes “1/(sin 54.7°)” of the thickness of the body region. In contrast, when the trench side wall face is vertical to the (0001) face, the channel length becomes equal to the thickness of the body region. In other words, if the channel mobility on the (03-38) face cannot be increased by at least 20% as compared with that on the vertical face to the (0001) face, even when the trench side wall face is the (03-38) face. Thus, the channel resistance cannot be reduced.
Also, for the sake of reducing the on-resistance, not only the channel resistance but also the degree of integration of channels is important. In a device such as trench MOSFETs, a specific structure is repeatedly integrated. Accordingly, the smaller the dimensions of the unit structure, the smaller the dimensions (cell pitch) of the unit structure into a repeating direction are. Thus, the degree of integration is improved, and the on-resistance becomes low.
FIGS. 9 and 10 each schematically show a cross-section shape of a trench. As is clear from the comparison of the both drawings, if the width of the trench bottom is identical, an opening width W1 of a trench 23, where a trench side wall face 21 is not vertical to a major face 22 of a substrate, is wider than an opening width W2 of a trench 25 when a trench side wall face 24 is vertical to the major face 22. Accordingly, when the trench side wall face 24 is inclined, the cell pitch becomes large. This will be concretely considered below while the foregoing (03-38) face is a trench side wall face as an example.
For simplicity, in FIG. 8, a so-called stripe-cell structure where the structure in the depth direction on the drawing does not change will be considered. Taking into consideration the thickness of the n-type source contact region 4, the thickness of the p-type body layer 3 and the preparation margin, the trench 6 is set have a depth of 3 μm. It is thought that a depth of 3 μm is a standard value in trench MOSFETs using SiC. Furthermore, as illustrated in FIG. 10, when the trench side wall face 24 is vertical to the major face 22, the cell pitch is set at 14 μm. When the mask alignment margin and the exposure boundary are supposed to be 2 μm, respectively, which is the minimum cell pitch that can be realized (as assumed by the present inventors). In such supposition, as illustrated in FIG. 9, when the trench side wall face 21 is the (03-38) face, the cell pitch is 18 μm, a value of that is increased by about 28% as compared with that in the case of FIG. 10.
Accordingly, when the trench side wall face is the (03-38) face, the on-resistance caused by the channel resistance is increased by 55% while increasing the cell pitch and the channel length. When the mask alignment margin and the exposure boundary are improved to 1 μm, a rate of increase of the on-resistance caused by the channel resistance reaches 90%. This is not limited to the stripe-cell structure but also is applicable to other structures, such as a hexagonal cell structure.
The aforementioned JP-A-2002-261275 discloses that the channel mobility on the (03-38) face is 86 cm2/Vs. On the other hand, it is reported that when the trench side wall face is a face vertical to the (0001) face, for example a (11-20) face, the channel mobility becomes approximately 65 cm2/Vs, as disclosed in Y. KANZAKI, et al, High channel mobilities of MOSFETs on highly-doped 4H-SiC (11-20) face by oxidation in N2O ambient, Materials Science Forum 2004, pages 1429 to 1432. It is noted from these values that in a trench MOSFET as designed in minimum dimensions when the mask alignment margin and the exposure boundary are 1 μm, respectively, the channel resistance when using the (03-38) face as the trench side wall face is approximately 40% higher than that when using the (11-20) face. Accordingly, when using the (11-20) face as the trench side wall face, the on-resistance becomes lower. Even if a face with high channel mobility is selected, low channel resistance cannot be always realized so that a structural factor of device must be taken into consideration.
In forming a trench in SiC, a plasma etching method is usually employed. Furthermore, under the existing circumstances, since it is difficult to prepare a lowly doped layer of SiC suitable as a drift layer with good reproducibility on an industrial scale by bulk growth, the drift layer is prepared by an epitaxial growth technique. Incidentally, in expressing Miller indices, “−” means a bar attached to an index just thereafter, and by attaching “−” before the index, it is meant that the index is a negative index.
According to the related-art technologies, however, in forming a trench by a plasma etching method, it is extremely difficult to uniformly keep the plasma conditions within a wafer face. For that reason, an angle of the trench side wall face against the major face (hereinafter referred to as “trench angle”) is scattered within the wafer face. Scattering the trench angle undesirably scatters the channel resistance, which scatters the on-resistance, leading to hindrance of practical implementation.
Also, to epitaxially growing an SiC layer with a suitable quality as a drift layer on a {0001} face of SiC, a large off angle is required. For example, 4H-SiC has large electron mobility and is highly expected as a semiconductor material for electric power. To epitaxially grow a high-quality SiC layer with good reproducibility on an industrial scale on a {0001} face of 4H-SiC, it is considered that an off angle of from 4 to 8 degrees is required, which not only scatters the trench angle within the foregoing wafer face, but also fluctuates the face azimuth of the trench side wall face.
For example, in FIGS. 9 and 10, if an off direction of the substrate is a right direction on the drawing, the face azimuth of the trench side wall face in the left side is shifted into a positive direction corresponding to the off angle. On the other hand, the face azimuth of the trench side wall face in the right side is shifted into a negative direction corresponding to the off angle. In other words, where the off angle is 8 degrees, the face azimuth differs by 16 degrees between the trench in the left side and the trench in the right side.
Accordingly, there remains a need to put an SiC-made trench MOSFET into practice by reducing the channel resistance among a considerably wide trench angle range. The present invention addresses this need.